1. Field
The present invention relates to a non-diffusion-junction split-gate nonvolatile memory cell, associated arrays, as well as methods of manufacture and operation.
2. Description of Related Information
Nonvolatile memory cells having a floating gate for the storage of charges thereon to control the conduction of current in the channel region in the substrate of the semiconductive material are well known in the art. See, for example, U.S. Pat. No. 5,029,130 whose disclosure is incorporated herein by reference in its entirety. Structurally, nonvolatile memory cells using a floating gate for storage may be classified as either a stacked gate configuration or a split gate configuration. In a stacked gate, a control gate is positioned directly over the floating gate. In a split gate, the control gate has one portion over and another portion adjacent the floating gate, where the control gate controls one region of the channel and the floating gate controls another region of the channel.
In an article entitled “90-nm-node multi-level AG-AND type flash memory with cell size of true 2-F/sup 2//bit and programming throughput of 10 MB/s” by Y. Sasago et al., published in the 2003 IEDM Technical Digest, pp. 34.2.1-34.2.4 (also pp. 823-26), the authors described an AG (assist gate) AND-type array of floating gate nonvolatile memory cells. See also, the paper entitled “Self-boosted charge injection for 90-nm-node 4-Gb multilevel AG-AND flash memories programmable at 16 MB/s” by H. Kurata et. al, published in the 2004 Digest of Technical Papers—Symposium on VLSI Circuits, pp. 72-73.
AND arrays and cross-sectional views of arrays of floating gate nonvolatile memory cells disclosed in the aforementioned papers are shown on FIGS. 1A and 1B, respectively. The arrays are comprised of a plurality memory cells arranged in a plurality of rows and columns. Schematic diagrams and cross-sectional views illustrating alternating floating gate/control gate structures and associated differing voltage conditions required for operation are shown (i.e. FIG. 1A illustrates structure and voltage conditions for the program and read operations of Sasago et al., and FIG. 1B illustrates structure and voltage conditions for the program operation of Kurata et al.). However, these arrays are restricted by operation of selected control gates in association with shared floating gates, and require a wide variety of operating voltages to be maintained independently at specified values.
Many such AND arrays of the prior art are formed in a row or column direction with a bit line and a line connecting the respective control gates. One problem with these structures is that they must be fabricated to allow voltages for both the bit line and the control gate line to be set independently for each cell. With two such lines for each cell and where for non-volatile memory cells the lines must carry high voltages, there may be excessive voltage control lines required for the pitch of each cell. In addition, such AND-type structures are often uni-directional in operation.
Memory arrays in which the adjacent rows/columns are electrically connected at ends of the array are known. See, e.g. FIG. 2 of U.S. Pat. No. 6,825,084. Additionally, control gates that are substantially T shaped positioned between a pair of floating gates and having a portion over a channel region, and capacitively coupled to the pair of floating gates are also known in the art. See e.g. U.S. Pat. No. 6,151,248. Finally, fabrication of memory cells and arrays without diffused junctions/channel regions is also known, as this can achieve desirable process simplification. Drawbacks of these structures and arrays, however, include additional or complex fabrication processes and undesired operating functionality such as higher operating voltages, restricted read operations, etc., among other disadvantages.
Accordingly, there is a need to reduce manufacturing complexity, increase cell density, increase data storage density, and improve operation of nonvolatile memory devices.